This invention relates to a structure of a library used in circuit design of a semiconductor device.
Japanese Unexamined Patent Publication (A) No. H08-161389 discloses a method of calculating a delay time in signal transmission from an output terminal of a circuit cell to a branch node connected to the output terminal. Specifically, the method comprises the steps of obtaining a wire length from the output terminal of the circuit cell to each branch node connected to the output terminal, obtaining a total tree length of a tree forming an RC net (resistance-capacitance network) connected to the output terminal, calculating a ratio RW between the wire length and the total tree length, and calculating the delay time by the use of the ratio RW and the total tree length. In this case, the delay time is accurately calculated by calculating a variance V(RW) of RW or by clustering RW by the use of a standard deviation "sgr" of RW.
This invention relates to a library which is used in designing a logic circuit of a semiconductor device and which memorizes a delay value for each signal path of a circuit element of the logic circuit. As will later be described with reference to the drawing, the circuit element of the logic circuit is, for example, a unit logic gate having a plurality of inputs and a single output. The delay value for each signal path of the circuit element is different in object of delay calculation from the delay time on a wire from the output terminal of the circuit cell to the branch node connected to the output terminal in the above-mentioned publication. The above-mentioned publication does not disclose such library used in designing the logic circuit of the semiconductor device, such delay value for each signal path of the circuit element of the logic circuit, and any information related to the delay value.
A logic LSI or a logic circuit at a signal processing part of a memory LSI is produced by the steps illustrated in FIG. 1 by the use of logic synthesis software. A technique of designing the logic circuit will presently be described.
A designer of the logic LSI describes a circuit function for realizing a circuit specification by the use of a hardware description language (HDL) such as Verilog-HDL. Referring to FIG. 2, the circuit function is described by Verilog-HDL. Referring to FIG. 3, the circuit having the circuit function described by the HDL is logically synthesized using circuit elements registered in the library.
The library comprises circuit elements including fundamental logic gates such as a NAND gate and macroscopic elements, such as a register and an adder, having fundamental functions. The logic synthesis software selects desired circuit elements from the library and synthesizes the circuit having the circuit function described by the HDL. The logic synthesis not only realizes the circuit function or logic described by the HDL but also optimizes a circuit velocity, a circuit area, and the like.
Referring to FIG. 4, a conventional library 10xe2x80x2 used in the logic synthesis software includes a NAND gate and a part describing delay values of the NAND gate. The library 10xe2x80x2 memorizes a minimum delay MIN as a best value, a typical delay TYP as a moderate value, and a maximum delay MAX as a worst value for each signal path of the NAND gate. Thus, the delay values in the velocity of each circuit element are determined depending upon a load condition. When the logic synthesis software is executed to select the desired circuit elements which satisfy the logic described by the HDL, the logic synthesis software can be set to select those circuit elements such that a minimum delay time is achieved.
Referring to FIG. 5, preparation of the library will be described. A test chip is produced and subjected to measurement of a device parameter such as a transistor threshold level (Vth). From the distribution of the device parameter, the maximum value (MAX), the minimum value ((MIN), and the typical value (TYP) of the device parameter are determined. Through circuit simulation based on these values, the maximum value (MAX), the minimum value (MIN), and the typical value (TYP) are determined for the delay values of the circuit element. These values thus determined are memorized in the library.
On the other hand, the circuit element has a predetermined area. Therefore, it is possible to execute the logic synthesis software with a setting such that a circuit area is minimized instead of a signal delay time of the circuit.
In the conventional circuit design described above, the variation in delay value of the circuit element is contained in the library as the minimum value and the maximum value. In most cases, the maximum value is set so that the probability of occurrence of a greater delay is about 0.1% or less. Such setting is generally called xe2x80x9c3"sgr"xe2x80x9d. This is because, in normal distribution of Gaussian distribution, a deviation from an average is equal to or greater than three times a standard deviation "sgr" at a probability of 0.1% or less.
However, the variation in delay value of the circuit element is assumed to be an independent event. Then, consecutive appearance of those circuit elements (for example, gates) having the maximum values is rare. If a large number of stages of circuit elements are contained upon the logic synthesis, evaluation is inclined to a greater delay than that actually obtained at a certain probability when the LSI is produced.
Referring to FIG. 6, a five-stage inverter circuit will be described by way of example. In the illustrated example, an average delay for each stage and 3"sgr" are assumed to be equal to 100 ps and 10 ps, respectively. Assuming that the variation in delay value of each inverter has a normal distribution and is completely independent of that of any other inverter, the total distribution as a sum of the normal distributions of such independent events has a variance which can be represented by a sum of variances of the distributions. By the use of 3"sgr" values registered in the library as the maximum values, the maximum value in delay value of the inverter circuit is estimated to be 550 ps. In the normal distribution, the variance is equal to a square of the standard deviation. Therefore, the variation of 50 ps is {square root over ( )}5 times excessive estimation. This problem is pointed out in xe2x80x9cDesign of CMOS ULSIxe2x80x9d edited by Tetsuya lizuka, published by Baifu-kan, 1989, pp. 149-150.
In the conventional design technique, the independent variation in delay value of the signal path in each individual chip is considered by MIN, TYP, and MAX. However, no consideration is made about the independent variation in delay value of the signal path in each individual signal path in the LSI chip. Therefore, optimization of delay has been carried out by calculating a sum of the delay values defined in the library and by increasing the velocity of a slowest signal path. However, in the actual LSI, the variation in delay value of the signal path is independent in each individual path in the LSI chip. Therefore, the above-mentioned approach does not provide the optimization, as will presently be described. For convenience of description, each delay value is given by an integral multiple of 0.1 ns.
Referring to FIGS. 7A and 7B, it is assumed that a circuit having 1000 signal paths is synthesized by the logic synthesis software and that two circuit plans (a) and (b) are produced. Specifically, the plan (a) includes a single path having a delay of 5.1 ns and 999 paths having a delay of 4.9 ns while the plan (b) includes 1000 signal paths having a delay of 5.0 ns. In this event, the logic synthesis software selects the plan (a) as a best plan. However, if all of the signal paths have a variation of 0.2 ns as 3"sgr", at least one path has a delay of 5.2 ns in most of the semiconductor devices in case of the circuit of the plan (a). On the other hand, the circuit of the plan (b) will be operated with a delay of 5.1 ns in the half or more of the semiconductor devices.
The circuit of the plan (a) logically synthesized is not always an optimum circuit taking into account the large variation in delay value of the signal path across the LSI chip. In order to avoid such disadvantage, it is necessary to know the nature of the variation of the circuit elements of the semiconductor device across the chip. However, no appropriate method has been found yet. On the other hand, reduction in design rule of the semiconductor device brings about the increase in variation of the device parameter.
It is an object of this invention to provide a structure of a library used in logic synthesis software capable of producing an optimum logic for an actual semiconductor device having a variation.
It is an object of this invention to provide logic synthesis software capable of producing an optimum logic for an actual semiconductor device having a variation.
Other objects of this invention will become clear as the description proceeds.
Libraries according to this invention, computer-readable recording media according to this invention, and methods according to this invention are as follows:
(1) A library for use in designing a logic circuit of a semiconductor device, the logic circuit comprising a circuit element having signal paths, the library memorizing a delay value for each of the signal paths of the circuit element, wherein the library further memorizes a standard deviation of a variation of the delay value for each of the signal paths of the circuit element.
(2) A library as described in the paragraph (1), wherein the standard deviation of the variation of the delay value is a standard deviation of a position dependent component of the variation of the delay value for each of the signal paths of the circuit element, the position dependent component being dependent upon a position of the logic circuit within a wafer plane when the logic circuit is formed on the wafer plane as a result of logic synthesis.
(3) A library as described in the paragraph (2), wherein the standard deviation of the position dependent component of the variation of the-delay value is a standard deviation of the position dependent component dependent upon an occupied area of the logic circuit or a length of one side of the logic circuit when the logic circuit is formed on the wafer plane as a result of logic synthesis.
(4) A library as described in the paragraph (1), wherein the standard deviation of the variation of the delay value is a standard deviation of a random component of the variation of the delay value for each of the signal paths of the circuit element, the random dependent component being independent of a position of the logic circuit within a wafer plane when the logic circuit is formed on the wafer plane as a result of logic synthesis.
(5) A library for use in designing a logic circuit of a semiconductor device, the logic circuit comprising a circuit element having signal paths, the library memorizing a delay value for each of the signal paths of the circuit element, wherein the library further memorizes a variance of a variation of the delay value for each of the signal paths of the circuit element.
(6) A library as described in the paragraph (5), wherein the variance of the variation of the delay value is a variance of a position dependent component of the variation of the delay value for each of the signal paths of the circuit element, the position dependent component being dependent upon a position of the logic circuit within a wafer plane when the logic circuit is formed on the wafer plane as a result of logic synthesis.
(7) A library as described in the paragraph (6), wherein the variance of the position dependent component of the variation of the delay value is a variance of the position dependent component dependent upon an occupied area of the logic circuit or a length of one side of the logic circuit when the logic circuit is formed on the wafer plane as a result of logic synthesis.
(8) A library as described in the paragraph (5), wherein the variance of the variation of the delay value is a variance of a random component of the variation of the delay value for each of the signal paths of the circuit element, the random dependent component being independent of a position of the logic circuit within a wafer plane when the logic circuit is formed on the wafer plane as a result of logic synthesis.
(9) A computer-readable recording medium which records a library for use in designing a logic circuit of a semiconductor device, the logic circuit comprising a circuit element having signal paths, the library memorizing a delay value for each of the signal paths of the circuit element and a standard deviation of a variation of the delay value for each of the signal paths of the circuit element, the recording medium further recording a program for making a computer execute a logic synthesis operation in which logic synthesis of the logic circuit is carried out by the use of the library.
(10) A computer-readable recording medium which records a library for use in designing a logic circuit of a semiconductor device, the logic circuit comprising a circuit element having signal paths, the library memorizing a delay value for each of the signal paths of the circuit element and a variance of a variation of the delay value for each of the signal paths of the circuit element, the recording medium further recording a program for making a computer execute a logic synthesis operation in which logic synthesis of the logic circuit is carried out by the use of the library.
(11) A method of designing a semiconductor device, comprising the steps of:
preparing a library for use in designing a logic circuit of the semiconductor device, the logic circuit comprising a circuit element having signal paths, the library memorizing a delay value for each of the signal paths of the circuit element and a standard deviation of a variation of the delay value for each of the signal paths of the circuit element; and
carrying out logic synthesis of the logic circuit by the use of the library.
(12) A method of designing a semiconductor device, comprising the steps of:
preparing a library for use in designing a logic circuit of the semiconductor device, the logic circuit comprising a circuit element having signal paths, the library memorizing a delay value for each of the signal paths of the circuit element and a variance of a variation of the delay value for each of the signal paths of the circuit element; and
carrying out logic synthesis of the logic circuit by the use of the library.
The method may comprise the step of calculating the variance of the variation of the delay value for each signal path independent of an average of the delay values, multiplying the variance by a predetermined coefficient corresponding to a scheduled yield, adding a resultant product to a square root of the variance to produce a sum as a maximum value of the delay value of the signal path.
Alternatively, the method may comprise the step of calculating, with respect to a plurality of signal paths in a design unit to be subjected to logic synthesis, the variance of the variation of the delay values for each signal path independent of an average of the delay values, obtaining a distribution of the delay values for each signal path, preparing an evaluation function by a combination of the distributions of the delay values for the signal paths, and carrying out the optimization of logic synthesis on the basis of the evaluation function.
(13) A method of preparing a library for use in designing a logic circuit of the semiconductor device, the logic circuit comprising a circuit element having signal paths, the library memorizing a delay value for each of the signal paths of the circuit element, a first variance of a position dependent component of a variation of the delay value for each of the signal paths of the circuit element, and a second variance of a random component of the variation of the delay value for each of the signal paths of the circuit element, the position dependent component being dependent upon a position of the logic circuit within a wafer plane when the logic circuit is formed on the wafer plane as a result of logic synthesis, the random dependent component being independent of the position of the logic circuit within the wafer plane when the logic circuit is formed on the wafer plane as a result of logic synthesis, the method comprising the step of:
separating a device parameter of the semiconductor device to be designed into the position dependent component and the random component by wavelet transform to obtain the first and the second variances.
(14) A method as described in the paragraph (13), wherein separation of the device parameter into the position dependent component and the random component by the wavelet transform is carried out based on judgment utilizing transform level dependency of a wavelet coefficient.
(15) A method as described in the paragraph (14), wherein the wavelet transform is carried out by the use of the Haar function.
(16) A method as described in the paragraph (13), wherein the wavelet transform compensates data at an unmeasurable position with any one of an average of overall data and an average of neighborhood data.
The library according to this invention includes as one of elements the standard deviation or the variance of the random component of the variation of the delay values of the circuit element such as a unit logical gate. Therefore, even in the semiconductor device using a production process accompanied with a large variation, it is possible to design a circuit close to an optimum circuit.
The library according to this invention includes as one of elements the standard deviation or the variance of the position dependent component of the variation of the delay values of the circuit element which is dependent upon the area or the length of one side of an occupied region of the circuit element obtained as a result of logic synthesis. Therefore, particularly in an asynchronous circuit, it is possible to design a circuit close to an optimum circuit in an actual semiconductor device.
In the method of preparing the library, the device parameter, such as a transistor threshold value, used in circuit design is separated into the position dependent component and the random component by the use of the wavelet transform. Therefore, with respect to the variation of the device parameter resulting from a complicated semiconductor process, the variation can be decomposed in mode into different components.
In the semiconductor design software or the method of designing a semiconductor device according to this invention, the logic synthesis is performed by the use of the library containing the above-mentioned variation. Therefore, a circuit close to the optimum circuit in the actual semiconductor device can be obtained as a result of the logic synthesis.
In the method of designing a semiconductor device according to this invention, the variance of the delay values for each signal path is calculated independent of the average of the delay values. The variance is multiplied by the predetermined coefficient corresponding to the scheduled yield. The resultant product is added to the square root of the variance to obtain the sum as the maximum value of the delay values of the signal path. Therefore, it is possible to reduce the amount of calculation and to obtain a circuit close to the optimum circuit in the actual semiconductor device.
In the method of designing a semiconductor device according to this invention, the variance of the variation of the delay values for each signal path is calculated independent of the average of the delay values with respect to a plurality of signal paths in the design unit to be subjected to logic synthesis. The distribution of the delay values for each signal path is obtained. The evaluation function is prepared by a combination of the distributions of the delay values for the signal paths. The optimization of logic synthesis is performed on the basis of the evaluation function. Therefore, it is possible to obtain a circuit close to the optimum circuit more accurately.
In the method of preparing a library according to this invention, the position dependent component and the random component of the variation are separated based on the judgment utilizing the transform level dependency of the wavelet coefficient. Therefore, it is possible to determine a separation point more accurately.
In the method of preparing a library according to this invention, the Haar function is used as the wavelet transform. Therefore, it is possible to calculate the chip size dependency of the variation in the position dependent mode simultaneously when the variation is separated in mode into different components.
In the method of preparing a library according to this invention, the data at the unmeasurable position are compensated by the average upon the wavelet transform. Therefore, the wavelet transform can be carried out for data in a generally circular shape such as a wafer or data with a partial lack.
The semiconductor device designed by the use of the software according to this invention is higher in performance than the conventional semiconductor device. By the use of the semiconductor device, a high-performance system can be produced.